The present invention relates to a solid-state imaging device wherein photoelectric conversion elements and charge transfer devices for extracting signal charges from the respective elements are integrated on a semiconductor substrate.
Solid-state imaging devices that use charge coupled devices (hereinafter abbreviated CCDs) as the charge transfer devices have been developed.
CCD imaging devices have high effective sensitivity because of their low noise characteristics and hold promise as a major solid-state imaging device in the future. The CCD imaging device is roughly classified into frame-transfer and interline types. The frame-transfer type has three essential drawbacks: (i) it requires not only an image area but also a storage area and therefore involves large chip size and low yield, (ii) a large number of pixels must be arranged in the horizontal direction to obtain the specified resolution, and (iii) low sensitivity. Accordingly, R&D efforts have in recent years been directed to the interline type that does not possess any of these drawbacks. A description of the interline type CCD imaging device is given in the Preprint of the 1980 Symposium of the Inst. of Television Engineers of Japan, pp. 33-34.
FIGS. 1A and 1B show the basic construction of an interline type CCD imaging device In FIG. 1A, the reference numeral 1 designates a photoelectric conversion element which consists of a photodiode, for example. Numerals 2 and 3 denote vertical and horizontal CCD shift registers which serve to carry optical signals from the photoelectric conversion elements to output terminal 4. Sets of devices 5-1 through 5-4 and 6-1 to 6-2 are clock pulse generators for the vertical and horizontal shift registers, respectively. Although in this example a four-phase and a two-phase clock pulse generator are used for vertical and horizontal shift registers, respectively, either four-phase or two-phase clock formats may be generally adopted. Numeral 7 represents a transfer gate that transfers the charge stored in the photodiode to vertical shift register 2. This device, which is a black-and-white imaging device, can be also used for color imaging by layering a color filter on it to provide each photodiode with color information. FIG. 1B shows a cross section of a pixel. Photodiode 1 is made of an n-type impurity semiconductor, for example. The symbol 2-1 denotes one of the electrodes constituting the vertical CCD shift register; symbol 2d indicates an impurity layer (for example, n-type) to form the vertical CCD shift register channel into the buried type (this layer is not required for a surface type channel); numeral 8 represents a p-type substrate, for example, numeral 9 designates a gate oxide film (e.g. a thin SiO.sub.2 film) that insulates the electrode from the substrate, and 10 indicates a field oxide film (e.g. a thick SiO.sub.2 film) for pixel isolation.
As stated above, the interline type is advantageous over the frame-transfer type in that it is suitable for mass production because of its small chip size, requires only a small number of horizontal pixels (about one-third the number of horizontal pixels required for the frame-transfer type), and has high sensitivity. However, even the interline type is inferior in performance to image pickup tubes used for the current television broadcasting, and poses the following difficult problems to be solved.
(1) Interlaced scanning is carried out in the vertical direction. In this imaging device, by way of example, the pixel signals in odd-numbered rows (1, 3, 5, . . . , 2N-1) are read out in the first field and those in the even-numbered rows (2, 4, 6, . . . , 2N) are read out in the second field. As a result, in the first field of the next frame, the signals for the rows not read out in the preceding field (that is, odd-numbered rows) are read out in addition to the new signals (this phenomenon is usually called "image lag"). The solid-state imaging device which has a high switching speed features no image lag. In actuality, however, it involves image lag attributable to the interlaced read-out system as described above. The rate of this image lag is as high as 50% and greater than that for electron tubes. This is the rate offensive to the human eye.
(2) In the vertical direction, filters of the same color are provided over two rows of pixels. Therefore, in the vertical direction, in spite of employing interlaced scanning and checkerboard color filters (which has filters colored green, the primary component of the luminance signal, double as many as red or blue filters), the device can offer only a resolution corresponding to half of the number of pixels, resulting in degraded picture quality. This limitation, along with the image lag described in (1), hinders the solid-state imaging device from being put to practical use.
(3) When a complementary color filter with high transmittance is used to improve the sensitivity, moire due to color signal operation is generated to degrade the picture quality. (When a primary color filter consisting of red, blue, and green filters with low transmittance is used, however, the amount of moire generated is small.)
It was found that to solve the above problems it is necessary to read out signals from two vertically adjacent rows of photodiodes simultaneously and to transfer the signals through different vertical CCD shift registers. In this description, "to read out signals from two rows of photodiodes simultaneously" means to output both signals for two adjacent scanning lines from the imaging device within the same horizontal scanning period. One of the inventors, with assistance from his co-workers, proposed an interline type CCD imaging device as shown in FIG. 2. (Refer to Japanese utility model registration application No. 56-149492: laid open No. 58-56458. Corresponding foreign applications are U.S. Ser. No. 423,466; European patent application No. 82109194.9, Publication No. 0077003: Canadian patent application No. 413037: Korean patent application No. 82-4547.) In FIG. 2, symbols 2-1 and 2-2 designate a pair of opposing vertical CCD shift registers, and numeral 11 is an insulator that electrically separates the CCD shift registers from each other. Signals from two vertically adjacent rows, for example, the rows represented by photodiodes (1-1, 1-2), and (1-3, 1-4), are transferred toward different vertical CCD shift registers toward the horizontal CCD. The signals delivered from vertical CCD shift registers 2-1 and 2-2 are further transferred to output terminals 4-1 and 4-2 through horizontal CCD shift registers 3-1 and 3-2, respectively.
It was found from actual evaluation that the above-mentioned problems can be solved by employing this 2-column vertical CCD system. However, this system has given rise to new problems such as reduced photodiode area (reduction in the amount of data (signals) stored and narrowed dynamic range), and reduction in area exposed to light (aperture) and restricted sensitivity despite the use of a complementary color filter. In efforts to solve these problems, we arrived at the concept of "reading out two lines simultaneously using one column of vertical CCD shift registers". One way to embody this concept is to use three-phase drive vertical CCD shift registers, store signal in one of the three electrodes, and transfer the signal successively. The frame-transfer type has prospects of three-phase drive because it has a relatively large space of imaging area. On the contrary, for the interline type, it is difficult to implement a three-phase drive system for the following reasons: (i) Both vertical CCDs and photodiodes occupy the same area, leaving little space in reserve; (ii) Unlike in the case of conventional four- or two-phase drive (even number of phases), all clock wires cannot be regularly arranged in the vertical direction. In the case of three-phase drive, the wire for one of the three phases is inevitably laid in an irregular fashion (for example, routed every one row or through the centers of the photodiodes), resulting in light sensitivity irregularities and flickers. Moreover, the wiring for this phase is inevitably ununiform because of the level difference between the wire and the wires for the remaining two phases, causing light sensitivity irregularities; (iii) A slight three-phase electrode mask misalignment in the fabrication process also results in sensitivity irregularities. As a result, the implementation of simultaneous two-line read-out system using a three-phase drive interline type requires well-designed device composition and construction.